New microfabrication techniques have been developed recently with higher integration and enhanced performance of semiconductor integrated circuits (hereinafter, referred to as “LSI”). CMP is one of such techniques, which is frequently used in a process of manufacturing LSIs (particularly in planarization of interlayer insulating materials, formation of metal plugs, formation of embedded wirings, and the like in a process for forming multilayer wiring).
With higher integration or enhanced performance of LSIs, micronization of pattern rule is also required. An example of the process that has been attracting attention recently is a double patterning process (see, for example, Patent Literature 1 below). In the double patterning process, the first pattern is formed by the first exposure and development, and then, the second pattern is formed on, for example, space portions in the first pattern by the second exposure and development.
Some processes have been suggested as a method for double patterning (see, for example, Patent Literature 2 below). One of examples of double patterning will be described by way of FIG. 1. First, a base having a substrate 1 and silicon oxide 2 is provided wherein the silicon oxide 2 has a prescribed pattern and is also formed on the substrate 1 (FIG. 1(a)). Next, a photoresist 3 is formed on the substrate 1 and silicon oxide 2 (FIG. 1(b)). The whole of the surface layer portion of the photoresist 3 is removed by dry etching so that a prescribed thickness of the photoresist 3 remains on silicon oxide 2 (FIG. 1(c)). A prescribed part of the photoresist 3 on silicon oxide 2 is removed through the exposure and development steps to thereby form a groove 4 in the photoresist 3 (FIG. 1(d)). The part of silicon oxide 2 exposed in the groove 4 is removed by dry etching (FIG. 1(e)). The photoresist 3 is peeled off to obtain silicon oxide 2 having a prescribed pattern (FIG. 1(f)).